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mitsubishi lsis mh32v725bst -5, -6 preliminary spec. mitsubishi electric 27/jul./1998 hyper page mode 2415919104 - bit ( 33554432 - word by 72 - bit ) dynamic ram mit - ds - 0237-0.0 description the mh32v725bst is 33554432-word x 72-bit dynamic ram stacked structural module. this consist of thirty-six industry standard 16m x 4 dynamic rams in tsop and two industry standard input buffer in tssop. the mounting of tsop on a card edge dual in-line package provides any application where high densities and large of quantities memory are required. this is a socket-type memory module ,suitable for easy interchange or addition of module. features MH32V725BST-5 type name /ras access time (max.ns) /cas address /oe cycle power access time (max.ns) access time (max.ns) access time (max.ns) time (min.ns) dissipation (typ.w) 50 19 30 19 21 84 104 utilizes industry standard 16m x 4 rams soj and industry standard input buffer in tssop 168-pin (84-pin dual dual in-line package) single 3.3v(?0.3v) supply operation low stand-by power dissipation . . . . . . . . . . 135.7mw(max) low operation power dissipation mh32v725bst -5 . . . . . . . . . . . . . . . . . . 14.96w(max) mh32v725bst -6 . . . . . . . . . . . . . . . . . . 13.66w(max) all input are directly lvttl compatible all output are three-state and directry lvttl compatible includes(0.22 uf x 38) decoupling capacitors 4096 refresh cycle every 64ms (cbr ref) 8192 refresh cycle every 64ms (ras only ref,normal r/w) hyper-page mpde,read-modify-write,/cas before /ras refresh, hidden refresh capabilities jedec standard pin configration & buffered pd pin buffered input except /ras and dq gold plating contact pads application main memory unit for computers , microcomputer memory pd&id table pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8 id0 id1 - 6 - 5 1 = nc , 0 = drive to vol pd pin . . . buffered. when /pde is low, pd information can be read id pin . . . non-buffered 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 1 1 0 0 0 12.8 11 pin configuration 1pin 10pin 11pin 40pin 41pin 84pin 85pin 94pin 95pin 124pin 125pin 168pin front side back side mh32v725bst-6 60 21 35 1
mitsubishi lsis mh32v725bst -5, -6 preliminary spec. mitsubishi electric 27/jul./1998 hyper page mode 2415919104 - bit ( 33554432 - word by 72 - bit ) dynamic ram mit - ds - 0237-0.0 pin configuration reserved: reserved use rfu: reserved for future use pin no. pin name pin no. pin name pin no. pin name pin no. pin name 9 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 51 85 86 87 88 89 90 91 92 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 93 127 128 129 130 131 132 133 134 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 135 reserved vss dq36 dq37 dq38 dq39 vcc dq40 dq41 dq42 dq43 dq44 vss dq45 dq46 dq47 dq48 dq49 vcc dq50 dq51 dq52 dq53 vss reserved reserved vcc rfu rfu vss a1 a3 a5 a7 a9 vcc rfu b0 reserved reserved vss dq0 dq1 dq2 dq3 vcc dq4 dq5 dq6 dq7 dq8 vss dq9 dq10 dq11 dq12 dq13 vcc dq14 dq15 dq16 dq17 vss reserved vcc /we0 /cas0 /ras0 /oe0 vss a0 a2 a4 a6 a8 vcc rfu rfu dq26 vss /oe2 /ras2 /cas4 reserved /we2 vcc reserved reserved dq18 dq19 vss dq20 dq21 dq22 dq23 vcc dq24 rfu rfu rfu rfu dq25 dq27 dq30 vss dq28 dq29 dq31 vcc dq32 vss pd1 pd3 pd5 pd7 id0 vcc dq34 dq33 dq35 dq62 vss rfu reserved /pde vcc reserved reserved dq54 dq55 vss dq56 dq57 dq58 dq59 vcc dq60 rfu rfu rfu rfu dq61 dq63 dq66 vss dq64 dq65 dq67 vcc dq68 vss pd2 pd4 pd6 pd8 id1 vcc dq70 dq69 dq71 2 a10 a11 /ras1 /ras3 /cas5 reserved /cas1 a12
mitsubishi lsis mh32v725bst -5, -6 preliminary spec. mitsubishi electric 27/jul./1998 hyper page mode 2415919104 - bit ( 33554432 - word by 72 - bit ) dynamic ram mit - ds - 0237-0.0 block diagram a0 b0 a1 - a12 d0 - d8 d9 - d17 d0 - d35 . . . vcc vss c 1 - c 38 d0 - d35 & input buffer row address strobe input column address strobe input write control input output enable input data i/o address input power supply ground /ras /cas /we /oe a, b dq vcc vss pin name function 3 dq32 dq33 dq34 dq35 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dq12 dq13 dq14 dq15 dq8 dq9 dq10 dq11 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 /ras0 /cas0 /we0 /oe0 /ras /cas /w /oe dq1 ~dq4 d0 /ras /cas /w /oe dq1 ~dq4 d18 /ras /cas /w /oe dq1 ~dq4 d1 /ras /cas /w /oe dq1 ~dq4 d19 /ras /cas /w /oe dq1 ~dq4 d2 /ras /cas /w /oe dq1 ~dq4 d20 /ras /cas /w /oe dq1 ~dq4 d3 /ras /cas /w /oe dq1 ~dq4 d21 /ras /cas /w /oe dq1 ~dq4 d4 /ras /cas /w /oe dq1 ~dq4 d22 /ras /cas /w /oe dq1 ~dq4 d5 /ras /cas /w /oe dq1 ~dq4 d23 /ras /cas /w /oe dq1 ~dq4 d6 /ras /cas /w /oe dq1 ~dq4 d24 /ras /cas /w /oe dq1 ~dq4 d7 /ras /cas /w /oe dq1 ~dq4 d25 /ras /cas /w /oe dq1 ~dq4 d8 /ras /cas /w /oe dq1 ~dq4 d26 /cas1 /ras1 dq68 dq69 dq70 dq71 dq64 dq65 dq66 dq67 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dq36 dq37 dq38 dq39 /ras2 /cas4 /we2 /oe2 /ras /cas /w /oe dq1 ~dq4 d9 /ras /cas /w /oe dq1 ~dq4 d27 /ras /cas /w /oe dq1 ~dq4 d10 /ras /cas /w /oe dq1 ~dq4 d28 /ras /cas /w /oe dq1 ~dq4 d11 /ras /cas /w /oe dq1 ~dq4 d29 /ras /cas /w /oe dq1 ~dq4 d12 /ras /cas /w /oe dq1 ~dq4 d30 /ras /cas /w /oe dq1 ~dq4 d13 /ras /cas /w /oe dq1 ~dq4 d31 /ras /cas /w /oe dq1 ~dq4 d14 /ras /cas /w /oe dq1 ~dq4 d32 /ras /cas /w /oe dq1 ~dq4 d15 /ras /cas /w /oe dq1 ~dq4 d33 /ras /cas /w /oe dq1 ~dq4 d16 /ras /cas /w /oe dq1 ~dq4 d34 /ras /cas /w /oe dq1 ~dq4 d17 /ras /cas /w /oe dq1 ~dq4 d35 /cas5 /ras3 d18 - d26 d27 - d35 d : m5m467405btp
mitsubishi lsis mh32v725bst -5, -6 preliminary spec. mitsubishi electric 27/jul./1998 hyper page mode 2415919104 - bit ( 33554432 - word by 72 - bit ) dynamic ram mit - ds - 0237-0.0 function the mh32v725bst provide, in addition to normal read, write, and read-modify-write operations, a number of other functions, e.g., hyper page mode, /cas before /ras refresh, and delayed-write. the input conditions for each are shown in table 1. table 1 input conditions for each mode operation /ras /cas inputs input/output refresh remark /w row address address column output read write (early write) write (delayed write) read-modify-write /cas before /ras refresh standby hidden refresh act act act act act act nac act act act act act act dnc nac act act act dnc nac dnc apd apd apd apd dnc dnc dnc opn vld ivd vld vld opn opn no no no no yes yes no hyper page mode identical note : act : active, nac : nonactive, dnc : don' t care, vld : valid, ivd : invalid, apd : applied, opn : open /oe act dnc dnc act act dnc dnc apd apd apd apd dnc dnc dnc input vld vld vld dnc dnc opn opn 4
mitsubishi lsis mh32v725bst -5, -6 preliminary spec. mitsubishi electric 27/jul./1998 hyper page mode 2415919104 - bit ( 33554432 - word by 72 - bit ) dynamic ram mit - ds - 0237-0.0 (ta = 0~70?, vcc = 3.3v +/- 0.3v, vss = 0v, unless otherwise noted) (ta=0~70?, vcc=3.3v +/- 0.3v, vss=0v, unless otherwise noted) (note 2) absolute maximum ratings symbol vcc io pd topr tstg parameter conditions ratings -0.5~4.6 50 38 0~70 -40~125 with respect to vss ta=25? supply voltage output current power dissipation operating temperature storage temperature recommended operating conditions unit limits min nom max v v v v 3.6 0 vcc+0.3 0.8 3.3 0 3.0 0 2.0 -0.3 parameter supply voltage supply voltage high-level input voltage, all inputs low-level input voltage vcc symbol vss vih vil (ta=0~70?, unless otherwise noted) (note 1) electrical characteristics capacitance symbol voh vol ioz i i icc1 (av) icc2 icc4(av) icc6(av) high-level output voltage parameter limits min max unit typ test conditions low-level output voltage off-state output current input current (except /ras) average supply current from vcc operating (note 3,4,5) (note 3,4,5) (note 3,5) supply current from vcc , stand-by average supply current from vcc hyper-page-mode average supply current from vcc /cas before /ras refresh mode ioh=-2.0ma iol=2.0ma q floating 0v vout vcc 0v vin vcc+0.3v, other input pins=0v /ras, /cas cycling trc=twc=min. output open /ras=/cas =vih, output open /ras=/cas vcc -0.2, output open /ras=vil,/cas cycling tpc=min. output open /cas before /ras refresh cycling trc=min. output open note 2: current flowing into an ic is positive, out is negative. 3: icc1 (av), icc4 (av) and icc6 (av) are dependent on cycle rate. maximum current is measured at the fastest cycle rate. 4: icc1 (av) and icc4 (av) are dependent on output loading. specified values are obtained with the output open. 5: under condition of colmun address being changed once or less while /ras=vil and /cas=vih i i (ras) input current (/ras) 0v vin vcc+0.3v, other input pins=0v 2.4 0 -20 -1 -90 vcc 0.4 20 1 90 v v a u ma ma ma ma limits min max unit typ pf pf pf ci ci (/ras) c(dq) symbol parameter test conditions input capacitance, /ras input input/output capacitance,data vi=vss f=1mhz vi=25mvrms input capacitance, except /ras input 21 78 29 unit v ma w ? ? - 6 - 6 - 6 5 1825 1825 1645 4687 4327 43 25 note 1 : all voltage values are with respect to vss vii vii vii vii vii vii iiv a u a u - 5 1645 - 5 - 5
mitsubishi lsis mh32v725bst -5, -6 preliminary spec. mitsubishi electric 27/jul./1998 hyper page mode 2415919104 - bit ( 33554432 - word by 72 - bit ) dynamic ram mit - ds - 0237-0.0 (ta=0~70?, vcc=3.3v +/- 0.3v, vss=0v, unless otherwise noted , see notes 6,14,15) switching characteristics note 6: an initial pause of 500 us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing a /cas before /ras refresh). note the /ras may be cycled during the initial pause . and any 8 /ras or /ras /cas cycles are required after prolonged periods (greater than 64 ms) of /ras inactivity before proper device operation is achieved. 7: measured with a load circuit equivalent to voh=2.4v(ioh=-2ma) and vol=0.4v(iol=-2ma) loads and 100pf. the reference levels for measuring of output signals are 2.0v(voh) and 0.8v(vol). 8: assumes that trcd trcd(max), tasc tasc(max) and tcp tcp(max). 9: assumes that trcd trcd(max) and trad trad(max). if trcd or trad is greater than the maximum recommended value shown in this table, trac will increase by amount that trcd exceeds the value shown. 10: assumes that trad trad(max) and tasc tasc(max). 11: assumes that tcp tcp(max) and tasc tasc(max). 12: toez (max), twez(max), toff(max) and trez(max) defines the time at which the output achieves the high impedance state (iout i +/- 10 uai) and is not reference to voh(min) or vol(max). 13: output is disable after both /ras and /cas go to high. limits parameter symbol unit - 5 min max - 6 min max tcac trac taa tcpa toea tohr tclz access time from /cas access time from /ras columu address access time access time from /cas precharge output hold time from /ras output low impedance time from /cas low access time from /oe (note 7,8) (note 7,9) (note 7,10) (note 7,11) (note 7) (note 13) (note 7) ns ns ns ns ns ns ns ns (ta=0~70?, vcc=3.3v +/- 0.3v, vss=0v, unless otherwise noted ,see notes 14,15) limits min max parameter symbol unit (note16) (note17) (note18) 64 31 19 timing requirements (for read, write, read-modify-write ,refresh, and hyper-page mode cycles) note 14: the timing requirements are assumed tt =2ns. 15: vih(min) and vil(max) are reference levels for measuring timing of input signals. 16: trcd(max) is specified as a reference point only. if trcd is less than trcd(max), access time is trac. if trcd is greater than trcd(max), access time is controlled exclusively by tcac or taa. . 17: trad(max) is specified as a reference point only. if trad trad(max) and tasc tasc(max), access time is controlled exclusively by taa. 18: tasc(max) is specified as a reference point only. if trcd trcd(max) and tasc tasc(max), access time is controlled exclusively by tcac. 19: either tdzc or tdzo must be satisfied. 20: either trdd or tcdd or todd must be satisfied. 21: tt is measured between vih(min) and vil(max). (note19) (note20) (note19) (note20) -5 min max 64 39 24 -6 tref trp trcd tcrp trpc tcpn trad tasr tasc trah tcah tdzc tdzo tcdd todd refresh cycle time /ras high pulse width delay time, /ras low to /cas low delay time, /cas high to /ras low delay time, /ras high to /cas low /cas high pulse width column address delay time from /ras low row address setup time before /ras low column address setup time before /cas low row address hold time after /ras low column address hold time after /cas low delay time, data to /cas low delay time, data to /oe low delay time, /cas high to data delay time, /oe high to data -6 30 8 11 8 4 2 8 6 0 -6 -6 19 19 -6 40 8 11 10 6 4 10 6 0 -6 -6 21 21 ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 19 31 34 5 50 11 19 21 36 39 5 60 11 21 6 tohc output hold time from /cas 11 11 iiv iiv iiv vii vii vii iiv iiv vii vii vii iiv iiv iiv toez toff trez output disable time after /cas high output disable time after /ras high output disable time after /oe high (note 12) (note 12,13) (note 12,13) ns ns ns ns 13 19 15 21 twez output disable time after /we high (note 12) (note21) 50 50 tt transition time 1 1 ns (note20) trdd delay time, /ras high to data 13 15 10 13 19 21 19 21
mitsubishi lsis mh32v725bst -5, -6 preliminary spec. mitsubishi electric 27/jul./1998 hyper page mode 2415919104 - bit ( 33554432 - word by 72 - bit ) dynamic ram mit - ds - 0237-0.0 read and refresh cycles limits parameter symbol unit -5 (note 22) write cycle (early write and delayed write) (note 22) 10000 10000 0 0 84 50 8 29 19 -6 31 19 13 min max limits parameter symbol unit (note 24) 10000 10000 ns ns ns ns ns ns ns ns ns ns ns ns 8 0 84 50 8 29 19 8 14 8 -6 14 twc tras tcas tcsh trsh twcs twch tcwl trwl twp tds tdh write cycle time /ras iow pulse width /cas iow pulse width /cas hold time after /ras iow write setup time before /cas low write hold time after /cas low /ras hold time after /cas low /cas hold time after /w low /ras hold time after w low data setup time before /cas low or w low data hold time after /cas low or w low write pulse width -5 min max note 22: either trch or trrh must be satisfied for a read cycle. -6 10000 10000 min max 10000 10000 10 0 104 60 10 34 21 10 16 10 -6 16 -6 min max trc tras tcas tcsh trsh trcs trch trrh tral torh tcal read cycle time /ras iow pulse width /cas iow pulse width /cas hold time after /ras iow read setup time after /cas high read hold time after /cas iow /ras hold time after /cas iow read hold time after /ras iow column address to /ras hold time /ras hold time after /oe iow column address to /cas hold time ns ns ns ns ns ns ns ns ns ns ns 0 0 104 60 10 34 21 -6 36 21 18 read-write and read-modify-write cycles limits parameter symbol unit min max -5 (note23) (note24) read write/read modify write cycle time /ras low pulse width /cas low pulse width /cas hold time after /ras low /ras hold time after /cas low read setup time before /cas low delay time, /cas low to /w low delay time, /ras low to /w low oe hold time after w low trwc tras tcas tcsh trsh trcs tcwd trwd tawd toeh ns ns ns ns ns ns ns ns ns (note24) (note24) 10000 10000 44 109 38 64 0 28 59 40 13 75 note 23: trwc is specified as trwc(min)=trac(max)+todd(min)+trwl(min)+trp(min)+4tt. 24:twcs, tcwd,trwd ,tawd and,tcpwd are specified as reference points only. if twcs twcs(min) the cycle is an early write cycle and the dq pins will remain high impedance throughout the entire cycle. if tcwd tcwd(min), trwd trwd (min), tawd tawd(min) and tcpwd tcpwd(min) (for fast page mode cycle only), the cycle is a read-modify-write cycle and the dq will contain the data read from the selected address. if neither of the above condition (delayed write) of the dq (at access time and until /cas or /oe goes back to vih) is indeteminate. min max -6 10000 10000 50 133 44 76 0 32 71 47 15 89 7 ns delay time, address to /w low iiv iiv iiv 13 toch /cas hold time after /oe iow ns 15
mitsubishi lsis mh32v725bst -5, -6 preliminary spec. mitsubishi electric 27/jul./1998 hyper page mode 2415919104 - bit ( 33554432 - word by 72 - bit ) dynamic ram mit - ds - 0237-0.0 hyper page mode cycle (read, early write, read -write, read-modify-write cycle, read write mix cycle,hi-z control by /oe or /w) (note 25) note 25: all previously specified timing requirements and switching characteristics are applicable to their respective hyper page mode cycle. 26: tras(min) is specified as two cycles of /cas input are performed. 27: tcp(max) is specified as a reference point only. limits parameter symbol min max (note26) 100000 /cas before /ras refresh cycle (note 28) limits parameter symbol unit min max note 28: eight or more /cas before /ras cycles instead of eight /ras cycles are necessary for proper operation of /cas before /ras refresh mode. -5 -5 min max 100000 -6 min max -6 unit ns ns ns ns ns ns thpc thprwc tdoh tras tcp tcprh hyper page mode read/write cycle time output hold time from /cas low /ras low pulse width for read write cycle /cas high pulse width /ras hold time after /cas precharge hyper page mode read write/read modify write cycle time 8 20 11 65 34 55 10 25 11 77 39 66 ns ns ns ns tcsr tchr trsr trhr /cas setup time before /ras low /cas hold time after /ras low read setup time before /ras low read hold time after /ras low 11 16 4 4 11 16 4 4 8 (note24) ns ns ns ns tcpwd tchol toepe twpe delay time,/cas precharge to /w low hold time to maintain the data hi-z until /cas access /oe pulse width(hi-z control) /w pulse width(hi-z control) 7 43 7 7 7 50 7 7 ns ns thcwd thawd delay time,/cas low to /w low after read delay time, address to /w low after read 28 40 32 47 ns ns ns ns thpwd thcod thaod thpod delay time,/cas precharge to /w low after read delay time,/cas low to /oe high after read delay time,address to /oe high after read delay time, /cas precharge to /oe high after read 25 43 13 28 30 50 15 33 (note27) 13 16
mitsubishi lsis mh32v725bst -5, -6 preliminary spec. mitsubishi electric 27/jul./1998 hyper page mode 2415919104 - bit ( 33554432 - word by 72 - bit ) dynamic ram mit - ds - 0237-0.0 9 timing diagrams (note 29) read cycle note 29 indicates the don't care input. v ih(min) v in v ih(max) or v il(min) v in v il(max) indicates the invalid output. vii vii vii vii dq (inputs) /ras /w dq (outputs) /oe / cas v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rad t rcd t csh t asc t cah t rcs t ras t rc t rsh t cas t ral t cac t aa t clz t rac t rch t rrh t asr t crp t rp hi-z hi-z row row address v ih v il address column address t dzc hi-z t oez t odd t oea t och t dzo t orh t rez t off t cal t ohr t ohc t cdd t wez data valid t rdd a0,b0~a12
mitsubishi lsis mh32v725bst -5, -6 preliminary spec. mitsubishi electric 27/jul./1998 hyper page mode 2415919104 - bit ( 33554432 - word by 72 - bit ) dynamic ram mit - ds - 0237-0.0 early write cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rcd t csh t asc t cah t wcs t ras t wc t rsh t cas t wch t asr t crp t rp hi-z row column row address data valid /ras /w v ih v il /oe address address t ds t dh /cas 10 dq (inputs) dq (outputs) a0,b0~a12
mitsubishi lsis mh32v725bst -5, -6 preliminary spec. mitsubishi electric 27/jul./1998 hyper page mode 2415919104 - bit ( 33554432 - word by 72 - bit ) dynamic ram mit - ds - 0237-0.0 delayed write cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rcd t csh t asc t cah t rcs t ras t wc t rsh t cas t asr t crp t rp hi-z row column row address data valid address address t clz t wch t cwl t rwl t dh t ds hi-z hi-z t wp t dzc v ih v il t oez t dzo t odd t oeh /ras /w /oe / cas 11 dq (inputs) dq (outputs) a0,b0~a12
mitsubishi lsis mh32v725bst -5, -6 preliminary spec. mitsubishi electric 27/jul./1998 hyper page mode 2415919104 - bit ( 33554432 - word by 72 - bit ) dynamic ram mit - ds - 0237-0.0 read-write, read-modify-write cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rcd t csh t asc t cah t rcs t ras t rwc t rsh t cas t asr t crp t rp hi-z row column row address data valid address address t clz t cwl t rwl t dh t ds hi-z hi-z t wp t dzc v ih v il t oez t dzo t odd t oeh t awd t cwd t rwd data valid t aa t cac t rac t oea t rad /ras /w /oe / cas 12 dq (inputs) dq (outputs) a0,b0~a12
mitsubishi lsis mh32v725bst -5, -6 preliminary spec. mitsubishi electric 27/jul./1998 hyper page mode 2415919104 - bit ( 33554432 - word by 72 - bit ) dynamic ram mit - ds - 0237-0.0 hyper page mode read cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rad t rcd t cah t ras t cp t cac t aa t rac t asr hi-z address column-1 row address t rp t cas row t asc t rcs hi-z t dzc v ih v il t dzo t oea t och data valid-1 t csh t hpc t cas t cp t cas t rsh column-2 column-3 t cah t asc t cah t asc t cprh t rch t rrh t cdd t cpa t oez t odd t rez t off t clz t doh t rdd t cac t aa data valid-2 t cpa t doh t cac data valid-3 t aa t cal t cal t cal t ohc t ohr t wez /ras /w /oe / cas 13 dq (inputs) dq (outputs) a0,b0~a12
mitsubishi lsis mh32v725bst -5, -6 preliminary spec. mitsubishi electric 27/jul./1998 hyper page mode 2415919104 - bit ( 33554432 - word by 72 - bit ) dynamic ram mit - ds - 0237-0.0 hyper page mode early write cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rcd t cah t ras t cp t asr address column-1 row address t rp t cas row t asc t wcs v ih v il t csh t hpc t cas t cp t cas t rsh column-2 column-3 t cah t cah t asc t asc hi-z t wch t wcs t wch t wcs t wch data valid-1 data valid-2 data valid-3 t ds t dh t ds t dh t ds t dh t cal t cal t crp /ras /w /oe / cas 14 dq (inputs) dq (outputs) a0,b0~a12
mitsubishi lsis mh32v725bst -5, -6 preliminary spec. mitsubishi electric 27/jul./1998 hyper page mode 2415919104 - bit ( 33554432 - word by 72 - bit ) dynamic ram mit - ds - 0237-0.0 t dzo hyper page mode read-write,read-modify-write cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rcd t cah t ras t cp t asr hi-z t rp t cas t asc t csh t hprwc t cas t rwl address column-1 row address row t cah t asc t rcs t rwd t dzc t ds column-2 t cwl t wp t rcs t wp t cwl hi-z hi-z t dh t ds t dzc t cpwd data valid-2 t dh hi-z hi-z t clz t dzo t oez t odd t oez t oeh v ih v il t rad t cwd t awd t awd t cwd t aa t cac data valid-1 t aa t cac data valid-2 t clz t rac t oea t cpa t oea t odd data valid-1 t crp /ras /w /oe / cas 15 dq (inputs) dq (outputs) a0,b0~a12
mitsubishi lsis mh32v725bst -5, -6 preliminary spec. mitsubishi electric 27/jul./1998 hyper page mode 2415919104 - bit ( 33554432 - word by 72 - bit ) dynamic ram mit - ds - 0237-0.0 t dzo t wch t dh hyper page mode mix cycle (1) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rad t rcd t cah t ras t cp t cac t aa t rac hi-z address column-1 row address t rp t cas row t asc t rcs t dzc v ih v il t dzo t oea t och data valid-1 t csh data valid-2 t hpc t cas t cp t cas column-2 column-3 t cah t asc t cah t asc t hprwc t cpwd t wp t wcs t ds t clz t cpa data valid-3 t aa t cal t cal t cwd t oez t odd t wez t oeh t oez t clz t oea t asr t crp t cac t odd t dh t ds data valid-3 t rwl t cwl t dz c t awd /ras /w /oe / cas 16 dq (inputs) dq (outputs) a0,b0~a12 note 30: /oe=l; /w hi-z control /oe=h; =/oe hi-z control
mitsubishi lsis mh32v725bst -5, -6 preliminary spec. mitsubishi electric 27/jul./1998 hyper page mode 2415919104 - bit ( 33554432 - word by 72 - bit ) dynamic ram mit - ds - 0237-0.0 t cpa data valid-1 v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t cah t asc v ih v il t hpc data valid-3 t aa t cac t oez t ds t odd data valid-2 hi-z t dh t dzc hi-z column-1 t cah t asc t cah t asc column-2 column-3 t aa t wch t cac t oea t clz hi-z t cpa t cal t cp t cas t rch t wcs t wez t cal hyper page mode mix cycle (2) t dzc t cas t hcod t haod t hpod t hcwd t hawd t hpwd /ras /w /oe / cas 17 dq (inputs) dq (outputs) a0,b0~a12 note 30: /oe=l; /w hi-z control /oe=h; =/oe hi-z control
mitsubishi lsis mh32v725bst -5, -6 preliminary spec. mitsubishi electric 27/jul./1998 hyper page mode 2415919104 - bit ( 33554432 - word by 72 - bit ) dynamic ram mit - ds - 0237-0.0 hyper page mode read cycle ( hi-z control by oe ) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rad t rcd t cah t ras t cp t cac t aa t rac t asr hi-z address column-1 row address t rp t cas row t asc t rcs hi-z t dzc v ih v il t dzo t oea data valid-1 t csh t hpc t cas t cp t cas t rsh column-2 column-3 t cah t asc t cah t asc t cprh t ral t rch t rrh t cdd t cpa t oez t odd t rez t off t clz t doh t rdd t cac t aa data valid-2 t cpa t oez t cac data valid-3 t aa t clz hi-z t oepe t chol t oepe t oez t oea t och data valid-1 t ohr t ohc t crp t wez /ras /w /oe / cas 18 dq (inputs) dq (outputs) a0,b0~a12
mitsubishi lsis mh32v725bst -5, -6 preliminary spec. mitsubishi electric 27/jul./1998 hyper page mode 2415919104 - bit ( 33554432 - word by 72 - bit ) dynamic ram mit - ds - 0237-0.0 hyper page mode read cycle ( hi-z control by w ) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rad t rcd t cah t ras t cp t cac t aa t rac t asr hi-z address column-1 row address t rp t cas row t asc t rcs hi-z t dzc v ih v il t dzo t oea t och data valid-1 t csh t hpc t cas t cp t cas t rsh column-2 column-3 t cah t asc t cah t asc t cprh t ral t rch t cdd t cpa t oez t odd t rez t off t clz t doh t rdd t cac t aa data valid-2 t cpa t wez t aa t cac data valid-3 t wpe t rch t rcs t clz hi-z t ohr t ohc t rrh t crp /ras /w /oe / cas 19 dq (inputs) dq (outputs) a0,b0~a12
mitsubishi lsis mh32v725bst -5, -6 preliminary spec. mitsubishi electric 27/jul./1998 hyper page mode 2415919104 - bit ( 33554432 - word by 72 - bit ) dynamic ram mit - ds - 0237-0.0 /cas before /ras refresh cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t ras t rc t asr t crp t rpc t rp row column address address t rc t ras t csr t chr t csr t rpc t cpn t rch t rcs hi-z v ih v il t oez t rp t chr t rez t rpc t rrh t off t ohr t ohc /ras /w /oe / cas 20 dq (inputs) dq (outputs) a0,b0~a12
mitsubishi lsis mh32v725bst -5, -6 preliminary spec. mitsubishi electric 27/jul./1998 hyper page mode 2415919104 - bit ( 33554432 - word by 72 - bit ) dynamic ram mit - ds - 0237-0.0 hidden refresh cycle (read) (note 31) note 31: early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. timing requirements and output state are the same as that of each cycle shown above. v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rad t rcd t cah t rcs t ras t rc t chr t cac t aa t clz t rac t rrh t asr t rp hi-z address column row address data valid t ras t rc t rp t rsh row t asc address t ral hi-z t dzc v ih v il hi-z t dzo t oea t orh t odd t oez t rez t cdd t rch t rdd t ohr t ohc t off /ras /w /oe / cas 21 dq (inputs) dq (outputs) a0,b0~a12
mitsubishi lsis mh32v725bst -5, -6 preliminary spec. mitsubishi electric 27/jul./1998 hyper page mode 2415919104 - bit ( 33554432 - word by 72 - bit ) dynamic ram mit - ds - 0237-0.0 133.35 17.78 6.77 max 5.1min 8.89 11.43 3 24.495 6.35 36.83 127.35 43.18 6.35 54.61 1.27 38.1 3 3 4 22 1.27

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